The present invention relates to device optimization, and more specifically, to minimizing variance of arrival times of waveforms in circuits in the presence of process environmental variations.
Circuit optimization includes, for example, minimizing variance of arrival times of waveforms in circuits in the presence of process voltage temperature variations. Process voltage temperature (PVT) conditions affect the performance of devices in a circuit. For example, changing the temperature of a device in a circuit changes the electrical properties of the device. The time delay of signal paths may be further affected by changes in the PVT conditions.
Many circuits use a system or reference clock to operate effectively. The reference clock outputs a clock signal that may be propagated through a variety of signal paths or branches in a circuit. The signal paths may include conductive interconnects or lines that connect a variety of devices such as field effect transistors that define the signal paths. The electrical properties of the signal paths may be different. For example, the physical length of interconnects between devices in a path, or the properties of a devices in the path may induce a time delay in the clock signal.